This invention is related to providing a system and control method therefor for transmitting/receiving data between microprocessors, and particularly to providing a system and control method therefor for performing data transmission/receive between indoor and outdoor microprocessors of an invertor room air-conditioner using the internal synchronizing clocks from the indoor microprocessor and dummy data previously stored in the microprocessors.
Data transmission/receive between microprocessors are generally dependent upon their interface input/output integrated circuit.
For example, Japanese Laid-Open Utility Model Publication No. 84-165047 relates to a synchronizing circuit of a signal processing device comprising a terminal for outputting a signal representing the interrupt ending state from a micro-computer which has the longest internal interrupt processing time among a plurality of micro-computers, and a gate circuit for prohibiting the supply of the interrupt signal when the terminal outputs the signal representing the interrupt ending state to supply it to micro-computers except for its own micro-computer. It is known that this circuit is related to the using of an external interrupt signal.
Also, Japanese Laid-Open Utility Model Publication No. 84-63751 concerns an interface circuit including a first switching element being enabled by data from a second micro-computer when the first micro-computer is at the data receiving condition, to reverse the data from the second micro-computer thereby to supply data to the first micro-computer, and a second switching element being enabled by data from the first micro-computer when the first micro-computer is at the data output condition, to reverse data from the first micro-computer thereby to feed data to the second micro-processor, thereby transmitting and receiving bilateral data between the first and the second micro-computers.
Also, a system for transmitting and receiving data between indoor and outdoor microprocessors is disclosed in an invertor room air-conditioner as shown in FIG. 1.
An indoor microprocessor 1 is provided with data input/output ports SI1 and SO1 connected to a data interface circuit, a synchronizing clock output port SCK1, an internal interrupt port R63 and an external interrupt port T2. The data output port SO1 is connected through a power source resistor R6 to a PNP type transistor TR1. The transistor TR1 is coupled at its emitter through a power source resistor R1, a diode D1 and a resistor R7 to the light emitting diode of a photo-coupler PC1, while being coupled through a resistor R2 to the transistor emitter of a photo-coupler PC2 grounded. The data input port SI1 is connected to the output terminal of a comparator COMP1 to receive the output signal therefrom, while the output signal is applied to the external interrupt port T2. The comparator COMP1 is tapped at its non-inverting terminal (+) by a resistor R3 between the transistor TR1 and the resistor R2, and the inverting terminal (-) is connected through a resistor R5 to a power source BDD. On the other hand, the collector of the transistor TR1 is connected through a resistor R4 to the inverting terminal (-) of the comparator COMP1, while being connected in common to the diode anode of the photo-couplers PC1 and PC3 and the transistor emitter of the photo-coupler PC2 to be grounded. The synchronizing clock port SCK1 is connected through a diode D5 and a resistor R8 to the diode of the photo-coupler PC3. The common line of the collector of the transistor TR1, the transistor emitter of the photo-couplers PC1 and PC2 and the diode of photo-coupler PC3 is grounded. Electrolysis condensers C2 and C3 and a diode D2 are coupled in parallel therebetween to separate the common line from the emitter signal line of the transistor TR1, while a diode D3 and a condenser C4 are coupled in parallel therebetween to separate it from the synchronizing clock port SCK1.
An outdoor microprocessor 2 includes data input/output ports SI2 and S)2 connected to a data interface circuit and a synchronizing clock input port SCK2. The data output port S02 is coupled through a resistor R13 to the base of a transistor TR2. The transistor TR2 is connected at its emitter to the transistor of the photo-coupler PC1, through a resistor R9 to the input port SI2, at its collector through a resistor R10 to the diode of the photo-coupler PC1, and then through the resistor R1 to the transistor emitter of the photo-coupler PC3. The photo-coupler PC3 is connected at its transistor emitter to the synchronizing clock port SCK2 and at its transistor collector to the power source VDD. Herein, the resistor R11 is grounded, and a resistor R12 and a condenser C5 are connected in parallel to teach other between the input line and the grounded line, so that the data input port SI2 is separated from the grounded line.
Such an invertor room air-conditioner performs an internal timer interrupt routine as follows, referring to FIGS. 2(A)-2(D).
An indoor microprocessor 1 checks the internal interrupt clock state at step 21 and outputs a high level signal, if the clock signal is low, or a low level signal at its interrupt port R63 to the synchronizing clock ports SCK1 and SCK2 of indoor and outdoor microprocessors 1 and 2, if the clock signal is high, through steps 22 and 23. For example, the signal from the internal interrupt port R63 is directly applied to the synchronizing clock port SCK1 and through the diode D5 and the resistor R8 to drive the diode of the photo-coupler PC3, so that the transistor of the photo-coupler PC3 is turned on to permit the synchronizing clock port SCK2 to receive the synchronizing clock pulses from the indoor microprocessor 1. At this time, the data transmission/receive state is set between the microprocessors 1 and 2 to perform the data transmission/receive main routine (shown in FIG. 2(A)).
With respect to the indoor microprocessor 1, at step 11 it is determined whether the pulse input from the serial output port S02 to the serial input port SI1 is a high level pulse having a 16 ms period. If it is a high level having a 16 ms period, control passes to step 12 to enable the external interrupt port T2. Otherwise, control is returned to the previous state operation.
When the external interrupt port T2 is once enabled, an external interrupt routine is performed as shown in FIG. 2B. At step 31, the external interrupt port T2 is disabled, at step 32 the serial input/output ports SI1 and S02 are enabled and at step 33 the microprocessor 1 is in the data transmission/receive state. In other words, when the output from the serial output SO1 is a high level signal to turn off the transistor TR1, the data signals from the serial output port S02 are applied through the transistor TR2 to turn on/off the photo-coupler PC2, and then through the resistors R2 and R3 to feed the data signals to the comparator COMP1, so that the comparator COMP1 output its compared signals to the serial input port SI1.
On the contrary, when the serial output port S02 outputs a high level signal to turn off the transistor TR2, the data signals from the serial output port SO1 are passed through the resistor R2, the diode D1 and the resistor R6 to turn on/off the photo-coupler PC1. At this time, the data signals are input to the serial input port SI2. Therefore, between the indoor and outdoor microprocessors 1 and 2, the data transmission/receive state is established.
Thereafter, as represented in FIG. 2D, at step 40 it is determined whether the receive mode is set at any one of the microprocessors 1 and 2. If in the receiving mode, control proceeds to step 41 to judge whether the third byte is received. If it is received, control passes to step 42 to disable the receiving mode and to enable the transmission mode. Then, at step 43, the first byte of transmission data is output to start the transmission mode at step 50.
If the receiving mode is not established at step 40, control jumps to step 44 to determine whether the third byte is transmitted. If not transmitted, control passes to step 45 to determine whether the second byte is transmitted. If the second byte is not transmitted, control passes to step 46 to output the second byte transmission data so as to start the transmission mode at step 50, and return, and if the second byte is transmitted, control passes to step 47 to output the third byte transmission data so as to start the transmission mode and return.
Furthermore, if the third byte is transmitted at step 44, control jumps to step 48 to disable the transmission mode and to prohibit the serial input/output ports at step 49. With it, the microprocessors 1 and 2 can transmit/receive data through their serial input/output ports SI1, SI2 and SO1 and S02.
As described above, the prior art commonly uses an external interrupt, which causes delays by the priority order processing during the processing of a plurality of interrupt signals in addition to the bit delay due to the clock synchronizing delay phenomena, which increases the possibility of making errors in the data transmission/receive.
Also, with respect to the hardware, the external interrupt is used to determine the initial synchronizing starting point of a system, however, this can lead to the external interrupt ports being initialized by exterior noises, thereby making system errors.
The prior art explained with reference to FIG. 1 must be provided with an external interrupt port for synchronizing any one of the indoor and outdoor microprocessors and an internal interrupt port mounted on any one of the microprocessors to generate the synchronizing clock for all the microprocessors. The data transmission/receive between microprocessors requires a plurality of interrupts with respect to its software in a manner that one microprocessor should transmit the high level signal of a 16 ms period to another microprocessor.
The object of the present invention is to provide a system and control method thereof for transmitting and receiving data between microprocessors without using an external interrupt.
Another object of the present invention is to provide a system and control method thereof for transmitting and receiving data using an internal clock of one of the microprocessors as a synchronizing clock signal between microprocessors.
Still another object of the present invention is to provide a system and control method thereof for transmitting and receiving data using dummy data previously input in indoor and outdoor microprocessors to prevent the noise errors during the reception of data by each of the microprocessors.